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Books

cover Dissertation: A Novel Compiler-Friendly Micro-Architecture for Rapid Development of High-Performance and Low-Power DSPs , published by Shaker Verlag , Aachen, ISBN 3-8322-3351-2
Several papers in Computer Systems: Architectures, Modeling, and Simulation , published by Springer Verlag , Heidelberg, ISBN 3-540-22377-0

Papers, first author

Date Conference / Journal Title
8/21/24 ICEF 2024 Efficient Euclidean Distance Computation for Smart Vehicle ADAS
6/4/2024 CMC 2024 Optimal Approximate Computation of Euclidean Distance in Spiking Neural P Systems
8/8/2019 CMC 2019 An Error-Tolerant Serial Binary Full-Adder via
a Spiking Neural P System using HP/LP Basic Neurons
3/19/14 MoK 2014 Formal Semantics of Synchronous Transfer Architecture
9/27/04 GSPX 2004 SAMIRA: A SIMD-DSP architecture targeted to the Matlab™ source language
9/8/2004 IEEE PARELEC 2004 Compiler Scheduling for STA-Processors
7/20/2004 SAMOS 2004 Synchronous Transfer Architecture (STA) (Springer Verlag )
7/23/2003 SAMOS 2003 MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code (Springer Verlag )
Apr. 2002 it+ti Journal Interface Based Design with Reusable Modules
3/15/2001 DATE 2001 Annotated Data Types for Addressed Token Passing Networks
8/7/2000 FDL 2000 Annotated Data Type Declarations for Bus Interface Synthesis

Papers, co-author

Date Conference / Journal First Author Title
3/2021 Journal of Membrane Computing Ganbat Ganbaatar Implementation of RSA Cryptographic Algorithm using SN P Systems based on HP/LP Neurons
2/2020 Journal of Membrane Computing Otogonnaran Orchibat An Error-Tolerant Serial Binary Full-Adder via Spiking Neural P System using HP/LP Basic Neurons
9/21/2016 MCSOC 2016 Lin Li A Data Locality and Memory Contention Analysis Method in Embedded NUMA Multi-core Systems
3/2008 Journal of Embedded Systems Pablo Robelly A HW/SW design methodology for embedded SIMD vector signal processors
2005 GI Jahrestagung 2005 Emil Matus A Compiler-friendly and Low-power DSP architecture
5/3/2005 SNUG Europe 2005 Hendrik Seidel Development and Implementation of a 3.6 GFLOP/s SIMD-DSP using the Synopsys Toolchain
3/19/2005 IEEE ICASSP 2005 Pablo Robelly Design and Automatic Code Generation of the LMS Algorithm for SIMD Signal Processors
Jan. 2005 Int. Journal of Embedded Systems Pablo Robelly A HW/SW Design Methodology for Embedded SIMD Vector Signal Processors
10/13/2004 IEEE SIPS 2004 Michael Hosemann Implementing a Receiver for Terrestrial Digital Video Broadcasting in Software on an Application Specific DSP
9/9/2004 IEEE PARELEC 2004 Hendrik Seidel Hardware / Software Co-design of a SIMD-DSP-based DVB-T Receiver
9/9/2004 IEEE PARELEC 2004 Pablo Robelly Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach
7/20/2004 SAMOS 2004 Hendrik Seidel Generated DSP Cores for Implementation of an OFDM Communication System
6/28/2004 IST-Summit 2004 Emil Matus Software Reconfigurable Baseband ASSP for Dual Mode UMTS/WLAN 802.11b Receiver
5/21/2004 IEEE ICASSP 2004 Pablo Robelly Implementation of Recursive Digital Filters into Vector SIMD DSP Architectures
11/24/2001 Globecom 2001 Winthir Brunnbauer Bringing two worlds together: AAL2 over IP

Patents

Number Title
US 6,675,283 Hierarchical connection of plurality of functional units with faster neighbor first level and slower distant second level connections
US 6,489,958 Method and device for graphic representation of an object defined by a plurality of triangles on a display surface
DE 10 2004 004 434.1 Method for the automatic creation of a processor using a machine description

 

  
           
 
 
 
 
   
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